NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 259

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.10.9
3.10.10
3.10.11
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
MSICAPID - Message Signalled Interrupt Capability ID
Register
MSINXPTR - Message Signalled Interrupt Next Pointer
Register
MSICTRL - Message Signalled Interrupt Control Register
Device:
Function:
Offset:
Version:
7:0
Device:
Function:
Offset:
Version:
7:0
Device:
Function:
Offset:
Version:
15:8
7
6:4
3:1
0
Bit
Bit
Bit
RO
RO
RO
RO
RW
RO
RW
Attr
Attr
Attr
8
0
58h
Intel 5000P Chipset
8
0
59h
Intel 5000P Chipset
8
0
5Ah
Intel 5000P Chipset
05h
6Ch
0h
0
000
0h
0
Default
Default
Default
CAPID: MSI Capability ID
This code denotes the standard MSI capability assigned by PCI-SIG
NXTPTR: MSI Next Pointer: The DMA Engine device is implemented as a PCI
Express device and this points to the PCI Express capability structure.
Reserved
AD64CAP:
All processors used with the Intel 5000P Chipset MCH do not support 64-bit
addressing, hence this is hardwired to 0
MMEN:
Software initializes this to indicate the number of allocate messages which is
aligned to a power of two.
one message to the device. See
interrupts are handled.
MMCAP:
The Intel 5000P Chipset MCH DMA Engine supports only one interrupt message
(power of two) for handling
MSIEN: MSI Enable
This bit enables MSI as the interrupt mode of operation instead of the legacy
interrupt mechanism.
0: Disables MSI from being generated.
1: Enables MSI messages to be generated for DMA related interrupts.
An extract of the flowchart of the DMA Engine error handling is given in
• DMA errors
• DMA completions
Multiple Message Enable
Multiple Message Capable
64-bit Address Capable
When MSI is enabled, the software will allocate at least
Section 3.10.13
Description
Description
Description
below for discussion on how the
Figure 3-7
259