NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 78
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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3.8.1.3.1
3.8.1.3.2
78
a. Even though the contents of the RID have an attribute as “RO”, it is ultimately dictated by the comparator flop
Stepping Revision ID (SRID)
The SRID is a 4-bit hardwired value assigned by Intel, based on product’s stepping. The
SRID is not a directly addressable PCI register. The SRID value is reflected through the
RID register when appropriately addressed. The 4 bits of the SRID are reflected as the
two least significant bits of the major and minor revision field respectively. See
Figure 3-3
Compatible Revision ID (CRID)
The CRID is an 4-bit hardwired value assigned by Intel during manufacturing process.
Normally, the value assigned as the CRID will be identical to the SRID value of a
previous stepping of the product with which the new product is deemed “compatible”.
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
3:0
Bit
(attribute “RWOST” in Device 0, function 0) that selects between the CRID/SRID outputs. The comparator is
set by BIOS/SW writing a specific value to offset 08h in dev0, fn 0 based on
if (DEV 0)
{RWOST}
{RO}
endif
Attr
else
0, 2-3, 8, 9
0
08h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
08h
Intel 5000Z Chipset
4-7
0
08h
Intel 5000P Chipset
16
0, 2
08h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset,
17
0
08h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
21
0
08h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
08h
Intel 5000P Chipset
Default
0h
Minor Revision
Incremented for each stepping which does not modify all masks. Reset for
each major revision.
0x0: M0 stepping
0x1: M1 stepping
0x2: M2 stepping
Others: Reserved
Note: The Metal steppings indicated are a subset of the Major revision. For
example, an A stepping with M0 as minor revision typically means A0.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Figure
3-3.
Register Description
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