NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 168

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.12.13
3.8.12.14
168
HDRLOG2[7:2, 0] - Header Log 2
HDRLOG3[7:2, 0] - Header Log 3
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
This register contains the third 32 bits of the header log.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
This register contains the fourth 32 bits of the header log.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:0
31:0
31:0
Bit
Bit
Bit
ROST
ROST
ROST
Attr
Attr
Attr
0, 2-3
0
120h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
120h
Intel 5000Z Chipset
4-7
0
120h
Intel 5000P Chipset
0, 2-3
0
124h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
124h
Intel 5000Z Chipset
4-7
0
124h
Intel 5000P Chipset
0, 2-3
0
128h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
128h
Intel 5000Z Chipset
4-7
0
128h
Intel 5000P Chipset
Default
Default
Default
0h
0h
0h
HDRLOGDW2: Header of TLP (DWORD 2) associated with error
HDRLOGDW3: Header of TLP (DWORD 3) associated with error
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
HDRLOGDW1: Header of TLP (DWORD 1) associated with error
Description
Description
Description
Register Description