NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 416
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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PCI Express Capability Structure
PEXLNKSTS[7:2, 0] - PCI Express Link Status Register
PEXSLOTCAP[7:2, 0] - PCI Express Slot Capabilities Register
PEXSLOTCTRL[7:2, 0] - PCI Express Slot Control Register
PEXSLOTSTS[7:2, 0] - PCI Express Slot Status Register
PEXRTCTRL[7:2, 0] - PCI Express Root Control Register
PEXRTSTS[7:2, 0] - PCI Express Root Status Register
PCI Express Advanced Error Reporting Capability
PEXENHCAP[7:2, 0] - PCI Express Enhanced Capability Header
UNCERRSTS[7:2] - Uncorrectable Error Status
UNCERRMSK[7:2] - Uncorrectable Error Mask
PCI Express Advanced Error Reporting Capability
UNCERRSEV[7:2] - Uncorrectable Error Severity
CORERRSTS[7:2, 0] - Correctable Error Status
CORERRMSK[7:2, 0] - Correctable Error Mask
AERRCAPCTRL[7:2, 0] - Advanced Error Capabilities and Control
HDRLOG0[7:2, 0] - Header Log 0
HDRLOG1[7:2, 0] - Header Log 1
HDRLOG2[7:2, 0] - Header Log 2
HDRLOG3[7:2, 0] - Header Log 3
RPERRCMD[7:2, 0] - Root Port Error Command
RPERRSTS[7:2, 0] - Root Error Status Register
RPERRSID[7:2, 0] - Error Source Identification Register
BNBSPCAPID[7:2, 0] - MCH Specific Capability ID
PEX_ERR_DOCMD[7:2, 0] - PCI Express Error Do Command Register
EMASK_UNCOR_PEX[7:2] - Uncorrectable Error Detect Mask
EMASK_COR_PEX[7:2, 0] - Correctable Error Detect Mask
EMASK_RP_PEX[7:2, 0] - Root Port Error Detect Mask
PEX_FAT_FERR[7:2, 0] - PCI Express First Fatal Error Register
PEX_NF_COR_FERR[7:2, 0] - PCI Express First Non-Fatal or Correctable
Error
Register
PEX_FAT_NERR[7:2, 0] - PCI Express Next Fatal Error Register
PEX_NF_COR_NERR[7:2, 0] - PCI Express Non Fatal or Correctable Next
Error
Register
PEX_UNIT_FERR[7:2, 0] - PCI Express First Unit Error Register
PEX_UNIT_NERR[7:2] - PCI Express Next Unit Error Register
Register
Register Name
Register Name
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4 5
Device
Intel® 5000Z Chipset Differences
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
Device
0
0
0
0
0
0
0
0
0
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
7Eh
80h
84h
86h
88h
8Ch
100h
104h
108h
Offset
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
168h
168h
Offset
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