NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 378
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Table 5-27. Intel 5000P Chipset MCH Frequencies for Processors and Core
Table 5-28. Intel 5000P Chipset MCH Frequencies for Memory
378
is common to both PCI Express agents, no phase matching between them is required
(plesiochronous mode). The Intel 5000P Chipset MCH core treats this frequency
domain asynchronously.
The BUSCLK and FBDCLK reference clocks are derived from the same oscillator. The
PECLK reference clock may be derived from a different oscillator.
The PCI Express interfaces operate asynchronously with respect to the core clock.
133 MHz
266 MHz
333 MHz
333 MHz
533 MHz
667 MHz
800 MHz
Core
DDR
FBD packet
FBD packet
FBD packet
Domain
Domain
BUSCLK
BUSCLK
BUSCLK
BUSCLK
FBDCLK
FBDCLK
FBDCLK
FSB 1X
FSB 2X
FSB 4X
FSB 1X
FSB 2X
FSB 4X
FSB 1X
FSB 2X
FSB 4X
FSB 1X
FSB 2X
FSB 4X
FBD U
FBD U
FBD U
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Frequency
Frequency
1,067 MHz
1333 MHz
133 MHz
266 MHz
533 MHz
266 MHz
533 MHz
167 MHz
333 MHz
667 MHz
333 MHz
667 MHz
266 MHz
133 MHz
333 MHz
167 MHz
400 MHz
200 MHz
3.2 GHz
4.0 GHz
4.8 GHz
Reference
Reference
BUSCLK
FBDCLK
Clock
Clock
Functional Description
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