NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 325

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.2.12.13
Table 5-10. Global Activation Throttling BW allocation as a function of GBLACTLM for a
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Disabling Closed/Open Loop Throttling
The following registers in the Intel 5000P Chipset can be initialized to disable throttling
(open/closed) if software desires to turn off throttling.
16384**1344 window with MC.GTW_Mode=0 (normal)
• THRTCTRL.THRMHIUNT = 0 /* This forces the Intel 5000P Chipset to ignore
• THRTHI.THRHILM = 0 (or 168d)
• THRTHI.THRMIDLM = 0 (or 168d)
• THRTLOW.THRLOWLM = 0 (or 168d)
• GBLACT.BLACTLM = 0 (or 168d) /*Above changes force Open loop throttling to be
GBLACTLM
GBLACT.
THRMTHRT by 2. By design THRMTHRT can never be below THRTHI. If the new
THRTHI is greater than THRMTHRT, then the algorithm will reset THRMTHRT to
THRTHI & the staircase function can no longer be used since the bottom (aka
ceiling) of THRTHI has already been reached as defined by the following equation
extracted from
temperature for closed loop */
off */
128
144
160 10485760
168 11010048
12
16
20
24
28
32
36
40
44
48
64
72
80
96
0 unlimited
1
2
3
4
5
6
7
8
Activates
THRMTHRT = max(THRMTHRT - 2, THRTHI)
1048576
1310720
1572864
1835008
2097152
2359296
2621440
2883584
3145728
4194304
4718592
5242880
6291456
8388608
9437184
# of
131072
196608
262144
327680
393216
458752
524288
786432
65536
Figure
5-12.
allowed
% BW
100.00%
11.90%
14.29%
16.67%
19.05%
21.43%
23.81%
26.19%
28.57%
38.10%
42.86%
47.62%
57.14%
76.19%
85.71%
95.24%
0.60%
1.19%
1.79%
2.38%
2.98%
3.57%
4.17%
4.76%
7.14%
9.52%
DIMM GB/s
BW per
0.03
0.06
0.10
0.13
0.16
0.19
0.22
0.25
0.38
0.51
0.63
0.76
0.89
1.02
1.14
1.27
1.40
1.52
2.03
2.29
2.54
3.05
4.06
4.57
5.08
5.33
sys BW , 1
DIMM/ch
10.16
12.19
16.25
18.29
20.32
21.33
0.13
0.25
0.38
0.51
0.63
0.76
0.89
1.02
1.52
2.03
2.54
3.05
3.56
4.06
4.57
5.08
5.59
6.10
8.13
9.14
sys BW 2
DIMM/ch
10.16
11.17
12.19
16.25
18.29
20.32
0.25
0.51
0.76
1.02
1.27
1.52
1.78
2.03
3.05
4.06
5.08
6.10
7.11
8.13
9.14
sys BW 4
DIMM/ch
10.16
12.19
14.22
16.25
18.29
20.32
0.51
1.02
1.52
2.03
2.54
3.05
3.56
4.06
6.10
8.13
325