NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 120

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.8.25
3.8.8.26
3.8.8.27
120
RBAR[7:2] - ROM Base Address Register
Not implemented in MCH, since the MCH is a virtual PCI-PCI bridge.
INTL[7:2,0] - Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between the initialization code and the device driver
dedicated interrupt line. This register RO and is provided for backwards compatibility
INTP[7:2,0] - Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the ESI port using the
appropriate Assert_Intx commands.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:0
7:0
Bit
Bit
RWO
Attr
Attr
RO
0, 2-3
0
3Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Ch
Intel 5000Z Chipset
4-7
0
3Ch
Intel 5000P Chipset
0, 2-3
0
3Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Dh
Intel 5000Z Chipset
4-7
0
3Dh
Intel 5000P Chipset
Default
Default
00h
01h
INTL: Interrupt Line
BIOS writes the interrupt routing information to this register to indicate which
input of the interrupt controller this PCI Express Port is connected to. Not used
in
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
BIOS/configuration Software has the ability to program this register once
during boot to set up the correct interrupt for the port.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
MCH
since the PCI Express port does not have interrupt lines.
Description
Description
.
The MCH does not have a
Register Description
.