NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 252

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.10
3.10.1
252
DMA Engine Configuration Registers
PCICMD: PCI Command Register
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:11
10
9
31:28
26:24
23:16
15:8
7:1
Bit
Bit
27
0
RV
RW
RO
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
RV
21
0
7Ch, 78h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
7Ch, 78h
Intel 5000P Chipset
8
0
04h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
0h
0
0
Default
Default
1010
000
00h
00h
0h
1
0
DTI: Device Type Identifier.
This field specifies the device type identifier. Only devices with this device-type will
respond to commands. “1010” specifies EEPROM’s. “0110” specifies a write-protect
operation for an EEPROM. Other identifiers can be specified to target non-EEPROM
devices on the SPD bus.
CKOVRD: Clock Override.
‘0’ = Clock signal is driven low, overriding writing a ‘1’ to CMD.
‘1’ = Clock signal is released high, allowing normal operation of CMD.
Toggling this bit can be used to “move” the port out of a “stuck” state.
SA: Slave Address.
This field identifies the DIMM EEPROM to be accessed through the SPD register.
BA: Byte Address.
This field identifies the byte address to be accessed through the SPD register.
DATA: Data.
Holds data to be written by SPDW commands.
Reserved
CMD: Command.
Writing a ‘0’ to this bit initiates an SPDR command. Writing a ‘1’ to this bit initiates
an SPDW command.
Reserved
INTxDisable: Interrupt Disable
This bit controls the ability of the DMA engine device to assert a legacy PCI
interrupt during DMA completions or DMA errors.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
FB2B: Fast Back-to-Back Enable
This bit does not apply to the DMA engine Device and hardwired to 0.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description