NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 338

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Note:
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“flush” all MSI writes from the root port that is, guarantee that all the MSI writes
pending in the MCH from the root port have been delivered to the local APIC in the
processor. To accomplish this flush operation, OS can perform a configuration read to,
say, the VendorID/DeviceID register of the root port and the expectation is that the
completion for this read will flush all the previously issued memory writes. The reason
the OS wants to flush is for cases where an interrupt source (like a root port) is being
retargeted to a different processor and OS needs to flush any MSI that is already
pending in the fabric that is still targeting the old processor.
As a case in point, reads to Intel 5000P Chipset MCH PCI Express (internal)
configuration spaces will not generally guarantee ordering of internal MSIs from a root
port/DMA Engine device as required since the Intel 5000P Chipset MCH uses a
configuration ring methodology which houses the registers for the various PCI Express
ports, MC, DMA Engine, Dfx and so forth) and it operates independently of the MSI/
interrupt generation logic. Thus any configuration ring access targeting a PCI Express
port registers will not necessarily order and align with the internal MSIs.
Solution: To mitigate this problem and enforce ordering of the MSIs, the Intel 5000P
Chipset MCH will implement a “pending MSI signal” that is broadcast from the MSI/
Hotplug blocks to the coherency engine and thereby block the configuration request
(non-posted) till all the MSI gets committed. Software will ensure that it will block
future MSI generation for that device when it issues the configuration read for that
device.
The CE will block sending any completion with the new bit-slice bit set when any of the
pending MSI wires is asserted. CE will not block other transactions or completions
during the block. When the pending MSI wires are deasserted, CE will be able to send
the configuration completions.
The Intel 5000P Chipset MCH Coherency Engine (CE) will block processor initiated MCH
configuration access completions (MMCFG or CFC/CF8) if there is a pending internally
generated MSI within the Intel 5000P Chipset MCH. (MSIs could be generated from the
DMA engine or the HotPlug-Pwr-Mgr-PEX Error block.
The pending MSI signal will be deasserted after fetch-completion is asserted for the
MSI from CE, that is, global visibility is guaranteed on the FSB. Then release the
configuration block and allow the configuration completion to flow through. This
approach will order the MSI and then send the non-posted configuration for that
device.
CE will add a bit-slice (one bit per table entry) to track processor initiated MCH
configuration access in CE transaction table. Note: Inbound configuration access will
not set this bit.
A defeature mode to control the MSI/NP_CFG ordering is defined in the
COHDEF.DIS_MSI_NPCFG register field.
Internal MSIs cannot be continuously generated since the corresponding status register
field needs to be cleared by software through configuration access before a new MSI
can be asserted.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Functional Description