NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 228

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.23.7
3.9.23.8
228
MTR[1:0][3:0] - Memory Technology Registers
These registers define the organization of the DIMM’s. There is one MTR for each pair of
slots comprising either one or two ranks. The parameters for these devices can be
obtained by serial presence detect.
MTR[3:0] defines slot-pairs [3:0] on branch[0]. MTR[7:4] defines slot-pairs [3:0] on
branch[1].
MTR[3:0] in
Section
MTR[3:0] in
Section
This register must not be modified while servicing memory requests.
DMIR[1:0][4:0] - DIMM Interleave Range
These registers define rank participation in various DIMM interleaves.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:9
3:2
1:0
Bit
8
7
6
5
4
3.9.23.7.
3.9.23.7.
Attr
RW
RW
RW
RW
RW
RW
RW
RV
21
0
8Ch, 88h, 84h, 80h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
8Ch, 88h, 84h, 80h
Intel 5000P Chipset
Table 3-24
Table 3-24
Default
00h
00
00
0
0
0
0
0
Reserved
PRESENT: DIMMs are present
This bit is set if both DIMMs are present and their technologies are compatible.
ETHROTTLE: Technology - Electrical Throttle
Defines the electrical throttling level for these DIMMs:
MC.ETHROT configuration field.
WIDTH: Technology - Width
Defines the data width of the SDRAMs used on these DIMMs
NUMBANK: Technology - Number of Banks
Defines the number of (real, not shadow) banks on these DIMMs
NUMRANK: Technology - Number of Ranks
Defines the number of ranks on these DIMMs.
NUMROW: Technology - Number of Rows
Defines the number of rows within these DIMMs.
NUMCOL: Technology - Number of Columns
Defines the number of columns within these DIMMs
is MTR[3:0] for Device 21 which is MTR[3:0] for this
is MTR[3:0] for Device 22 which is MTR[7:4] for this
‘0’ = Electrical Throttling is disabled
‘1’ = Electrical Throttling is enabled using the throttling level defined by the
‘0’ = x4 (4 bits wide)
‘1’ = x8 (8 bits wide)
‘0’ = four-banked
‘1’ = eight-banked
‘0’ = single ranked
‘1’ = double ranked
“00”= 8,192, 13 rows
“01”= 16,384, 14 rows
“10”= 32,768, 15 rows
“11”= Reserved
“00”= 1,024, 10 columns
“01”= 2,048, 11 columns
“10”= 4,096, 12 columns
“11”= Reserved
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description