NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 267
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Register Description
3.11.2
3.11.3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
DIO0IBSTAT: PCI Express IBIST Completion Status
Register
DIO0IBERR: PCI Express IBIST Error Register
Device:
Function: 0
Offset:
Version:
Device:
Function: 0
Offset:
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RWC
RWC
RWC
RWC
RWC
RWC
RWC
Attr
Attr
RO
RO
RO
RO
RO
RO
RO
RV
RV
0
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
0
394h
395h
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IBSTAT7: IBIST Status port 7
0: IBIST either has not started the first time or it is still running.
1: IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
IBSTAT6: IBIST Status port 6
0: IBIST either has not started the first time or it is still running.
1: IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
IBSTAT5: IBIST Status port 5
0: IBIST either has not started the first time or it is still running.
1: IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
IBSTAT4: IBIST Status port 4
0: IBIST either has not started the first time or it is still running.
1: IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
IBSTAT3: IBIST Status port 3
0: IBIST either has not started the first time or it is still running.
1: IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
IBSTAT2: IBIST Status port 2
0: IBIST either has not started the first time or it is still running.
1: IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
Reserved.
IBSTAT0: IBIST Status port 0
0: IBIST either has not started the first time or it is still running.
1: IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
P7ERRDET: Error Detected on port 7
P6ERRDET: Error Detected on port 6
P5ERRDET: Error detected on port 5
P4ERRDET: Error detected on port 4
P3ERRDET: Error Detected on port 3
P2ERRDET: Error Detected on port 2
Reserved
P0ERRDET: Error detected on port 0
Description
Description
267
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