NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 337

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Table 5-14. Chipset Generated Interrupts
5.8.1
5.8.1.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
The following table summarizes the different types of chipset generated interrupts that
were discussed. Although the interrupt and SW mechanism is flexible and can be
changed depending on how the system is hooked up, for reference this table also
describes what SW mechanism is expected to be used.
Chipset Error
PCI Express Error
PCI Express HP (PresDet
chg, Attn button, and so
forth.)
PCI Express HP from
downstream device
PCI Express HP from
downstream device
(non-native, Intel part)
PCI Express HP from
downstream device
(non-native, non-Intel
part)
Downstream PCI Hot-
Plug
Power Management
Event (PME)
Intel 5000P Chipset Generation of MSIs
The Intel 5000P Chipset MCH generates MSIs on behalf of PCI Express Hot-Plug events
if Intel 5000P Chipset MCH.MSICTRL.MSIEN is set. Refer to
5000P Chipset MCH will interpret PCI Express Hot-Plug events and generate an MSI
interrupt based on Intel 5000P Chipset MCH.MSIAR and Intel 5000P Chipset
MCH.MSIDR registers. When the Intel 5000P Chipset MCH detects any PCI Express Hot-
Plug event, it will generate an interrupt transaction to both processor buses. The
address will be the value in Intel 5000P Chipset MCH.MSIAR. The data value will be the
value in MSIDR.
Internal to the Intel 5000P Chipset MCH, the MSI can be considered an inbound write
to address MSIAR with data value of MSIDR, and can be handled the same as other
inbound writes that are MSIs or APIC interrupts.
MSI Ordering in Intel 5000P Chipset MCH
Ordering issues on internally generated MSIs could manifest in the Intel 5000P Chipset
MCH if software/device drivers rely on certain usage models, for example, interrupt
rebalancing, Hot-Plug to flush them. The producer-consumer violation may happen, if a
root port has posted an MSI write internally in the MCH and the software wants to
Source
management event, it will clear the PEXRTSTS.PMESTATUS bit (by writing 1), at
which point the Intel 5000P Chipset MCH can send Deassert_PMEGPE to ESI
port.
Intel 5000P Chipset MCH registers ERR[2:0], MCERR, Intel®
PCI Express ERR_COR/UNC/FATAL
message
Intel 5000P Chipset MCH registers
For card-these registers are set
via the VPP/SM bus interface.
For module- these registers are
set by inband Hot-Plug messages.
MSI
PCI Express Assert/Deassert GPE
Sideband signals directly to
Intel® 631xESB/632xESB I/O
Controller Hub
PCI Express Assert/Deassert GPE
PCI Express PM_PME message
Signalling mechanism
631xESB/632xESB I/O
Controller Hub Reset
ERR[2:0], MCERR, Intel®
631xESB/632xESB I/O
Controller Hub Reset
Deassert_intx, or
Assert_HPGPE,
Deassert_HPGPE
MSI interrupt (processor
bus)
Assert_GPE, Deassert_GPE
to ESI
N/A
Assert_GPE, Deassert_GPE
to ESI
Assert_PMEGPE,
Deassert_PMEGPE to ESI
MSI or Assert_intx,
Intel 5000P Chipset
signal method
Figure
5-14. The Intel
MCH
Any
Any
SCI->ACPI or
MSI
MSI
SCI->ACPI
SCI->ACPI
SCI->ACPI
SCI->ACPI
Expected SW
mechanism
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