NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 245

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.9.25.14
3.9.25.15
3.9.25.16
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
FBD[1:0]IBRXSHFT: IBIST Receive Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
FBD[3:2]LNERR: IBIST Receive Lane Error Register
This register enables IBIST operations for individual lanes.
FBD[1:0]LNERR: IBIST Receive Lane Error Register
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
31:14
31:14
12:0
12:0
12:0
Bit
Bit
Bit
13
13
13
RWST
RWST
RWST
RWST
ROST
ROST
Attr
Attr
Attr
RV
RV
22
21
22
298h, 198h
298h, 198h
29Ch, 19Ch
Default
Default
Default
0001h
0001h
0h
0h
0
0
0
0
rxinvshfthi: Receiver Inversion Shift Register for DFT
The pattern loaded in this bit field indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This bit location will experience
rotate-left-shift operation with bits[12:0].
rxinvshft: Receiver Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This register acts as a rotate-left
shift register regardless of the setting of RXINVSWPMD bit. The Modulo-5
value is used to compare each sub-section of the northbound lanes for error
checking.
Reserved
rxinvshfthi: Receiver Inversion Shift Register for DFT
The pattern loaded in this bit field indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This bit location will experience
rotate-left-shift operation with bits[12:0].
rxinvshft: Receiver Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This register acts as a rotate-left
shift register regardless of the setting of RXINVSWPMD bit. The Modulo-5
value is used to compare each sub-section of the northbound lanes for error
checking.
Reserved
rxerrstat: Receive error lane status for DFT.
This register records the error from lane 13 of this port.
rxerrstat: Receive error lane status.
This register records the errors from all lanes of this port.
Description
Description
Description
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