NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 110

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.8.9
3.8.8.10
110
PBUSN[7:2] - Primary Bus Number
This register identifies the bus number on the on the primary side (MCH) of the PCI
Express port.
SBUSN[7:2] - Secondary Bus Number
This register identifies the bus number assigned to the secondary side (PCI Express) of
the “virtual” PCI-PCI bridge. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to devices connected to PCI Express.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:2-3
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:0
7:0
Bit
Bit
Attr
Attr
RW
RO
2-3
0
18h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
18h
Intel 5000Z Chipset
4-7
0
18h
Intel 5000P Chipset
0
19h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
19h
Intel 5000Z Chipset
4-7
0
19h
Intel 5000P Chipset
Default
Default
00h
00h
PBUBSNUM: Primary Bus Number
Configuration software typically programs this field with the number of the bus
on the primary side of the bridge. Since the PCI Express virtual PCI-PCI bridge
is an internal device and its primary bus is consistently 0, these bits are read
only and are hardwired to 0.
SECBUSNUM: Secondary Bus Number
This field is programmed by configuration software with the lowest bus number
of the busses connected to PCI Express. Since both bus 0, device 1 and the
PCI to PCI bridge on the other end are considered by configuration software to
be PCI-PCI bridges, this bus number will consistently correspond to the bus
number assigned to the PCI Express port.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description