NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 341

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.11.1
5.11.1.1
5.11.1.2
5.11.2
5.11.3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Power Management Support
The Intel 631xESB/632xESB I/O Controller Hub provides a rich set of power
management capabilities for the operating system. The MCH receives PM_PME
messages on its standard PCI Express port and propagates it to the Intel 631xESB/
632xESB I/O Controller Hub over the ESI as an Assert_PMEGPE message. When
software clears the PEXRTSTS.PME Status register bit, in the PEXRSTSTS[7:2, 0] PCI
Express Root Status Register
generate a Deassert_PMEGPE message to the Intel 631xESB/632xESB I/O Controller
Hub. The MCH must also be able to generate the Assert_PMEGPE message when exiting
S3 (after the reset). The PMGPE messages are also sent using a wired-OR approach.
Rst_Warn and Rst_Warn_Ack
The Rst_Warn message is generated by the Intel 631xESB/632xESB I/O Controller Hub
as a warning to the MCH that it wants to assert PLTRST# before sending the reset. In
the past, problems have been encountered due to the effects of an asynchronous reset
on the system memory states. Since memory has no reset mechanism itself other than
cycling the power, it can cause problems with the memory’s internal states when clocks
and control signals are asynchronously tri-stated or toggled, if operations resume
following this reset without power cycling. To protect against this, the Intel 631xESB/
632xESB I/O Controller Hub will send a reset warning to the MCH. The Gold Bridge
(Advanced Memory Buffer) is supposed to handle putting the DIMMs into a non-lockup
state in the event the link “goes down” in the middle of DDR2 protocol. The Intel 5000P
Chipset MCH is NOT required to place quiesce the DRAM’s prior to reset.
The MCH completes the handshake by generating the Rst_Warn_Ack message to the
ICH6 at the earliest.
STPCLK Propagation
The Intel 631xESB/632xESB I/O Controller Hub has a sideband signal called STPCLK.
This signal is used to place IA32 CPUs into a low power mode. Traditionally, this signal
has been routed directly from the I/O Controller Hub to the CPUs.
In future ESBx components, the plan is to rearchitect the mechanism for alerting the
CPUs of a power management event. However, this chipset (using Intel 631xESB/
632xESB I/O Controller Hub) will require the same method used for past server
chipsets (route STPCLK on the board as appropriate). The MCH will not provide any
in-band mechanisms for STPCLK.
Special Interrupt Support
The Intel 631xESB/632xESB I/O Controller Hub integrates an I/O APIC controller. This
controller is capable of sending interrupts to the processors with an inbound write to a
specific address range that the processors recognize as an interrupt. In general, the
compatibility interface cluster treats these no differently from inbound writes to DRAM.
However, there are a few notable differences listed below.
Inbound Interrupts
To the MCH, interrupts from the Intel 631xESB/632xESB I/O Controller Hub are simply
inbound non-coherent write commands routed to the processor buses. The MCH does
not support the serial APIC bus.
,
after it has completed the PME protocol, the MCH will
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