NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 108

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.8.3
3.8.8.4
108
CLS[7:2, 0] - Cache Line Size
This register contains the Cache Line Size and is set by BIOS/Operating system. It does
not affect the PCI Express port functionality in the MCH.
PRI_LT[7:2, 0] - Primary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the primary interface. It does not affect/influence PCI Express functionality.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2:0
7:0
Bit
Bit
7
6
5
4
3
Attr
Attr
RW
RO
RO
RO
RO
RV
RV
0, 2-3
0
06h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
06h
Intel 5000Z Chipset
4-7
0
06h
Intel 5000P Chipset
0, 2-3, 0
0
0Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
0Ch
Intel 5000Z Chipset
4-7
0
0Ch
Intel 5000P Chipset
Default
Default
00h
0h
0
0
0
1
0
FB2B: Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0
Reserved. (by PCI SIG)
66MHZCAP: 66 MHz capable.
Not applicable to PCI Express. Hardwired to 0
CAPL: Capabilities List
This bit indicates the presence of PCI Express capabilities list structure in the
PCI Express port. Hardwired to 1. (Mandatory)
INTxSTAT: INTx Status
Indicates that an INTx interrupt message is pending internally in the PCI
Express port.
The INTx status bit should be rescinded when all the relevant events via RAS
errors/HP/PM internal to the port that requires legacy interrupts are cleared by
software.
Reserved. (by PCI SIG)
CLS: Cache Line Size
This is an 8-bit value that indicates the size of the cache line and is specified in
DWORDs. It does not affect the
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
MCH
Description
Description
.
.
.
Register Description