NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 123

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.8.29
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PEXLWSTPCTRL: PCI Express Link Width Strap Control Register
This register provides the ability to change the PCI Express link width through software
control. Normally, the Intel 5000P Chipset MCH will use the PEWIDTH[3:0] pins to train
the links. However, if BIOS needs the ability to circumvent the pin strappings and
enforce a specific setting for a given platform, it must perform a soft initialization
sequence through the following actions in this register:
The chipset will then use the values initialized in the PEXLWSTPCTRL.GPMNXT0(1)
fields and train the links appropriately following the hard reset. The Intel 5000P Chipset
MCH will also provide status information to the software as to what link width it is
currently using to train the link via PEXLWSTPCTRL.GPMCUR0(1) fields and the
appropriate training mode, PEXLWSTPCTRL.LWTM. (pins strap vs. software
enabled mode).
Device:
Function: 0
Offset:
15:14
13:11
10:8
7
6:4
1. Set PEXLWSTPCTRL.LWOEN to ‘1’.
2. Write the desired link width to PEXLWSTPCTRL.GPMNXT0(1) fields for IOU0 and
3. Perform a hard reset to the Intel 5000P Chipset MCH.
Bit
IOU1 clusters.
RV
RO
RO
RO
RWST
Attr
0
40h
0h
000
000
0
000
Default
Reserved
GPMCUR1: IOU1 max width Current Configuration Now (ports 4-7)
This field is updated by the hardware to indicate the current link width of IOU1
ports that is used for training. This field is set before training gets underway.
000: x4,x4,x4,x4
001: x8,--,x4,x4
010: x4,x4, x8,--
011: x8,--,x8,--
100: x16,--,--,--,--
others: Reserved
GPMCUR0: IOU0 max width Current Configuration (ports 2-3 only, port 0,
ESI, is always x4)
This field is updated by the hardware to indicate the current link width of IOU1
ports that is used for training. This field is set before training gets underway.
000: x4,x4
001: Reserved
010: x8,--
Others: Reserved
LWTM: Link Width Training Mode
This field is updated by the hardware to provide feedback to software on the
training mode it is using following reset. That is, link strap or soft initialization of
link widths.
0: IOU clusters trained the links using the PEWIDTH[3:0] pins (external strapping)
[default]
1: IOU clusters trained the links using the soft initialization mechanism in this
register viz. GPMNXT1 and GPMNXT0 following a hard reset.
GPMNXT1: IOU1 max width Configuration Next (ports 4-7)
The IOU1 cluster will use this field to train the link after a hard reset provided
LWOEN is set.
Refer to
page
126.
Table 3.8.8.30, “PEXCTRL[7,2:0]: PCI EXPRESS Control Register” on
Description
123