NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 347

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Table 5-1.
Note:
Note:
5.12.6
Table 5-15. Options and Limitations (Sheet 1 of 2)
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PCI Express Link Width Strapping Options for Port CPCI Configuration in MCH
Intel 5000V Chipset does not have PCI Express ports 4, 5, 6, and 7. So the only option
is to configure ports 2 and 3 as a single x8 or two x4 ports.
The PCI Express Base Specification, Revision 1.0a requires that a port be capable of
negotiating and operating at the native width and 1x. The Intel 5000P Chipset MCH will
support the following link widths for its PCI Express ports viz., x8, x4 and x1.During link
training, the MCH will attempt link negotiation starting from its native link width from
the highest and ramp down to the nearest supported link width that passes negotiation.
For example, a port strapped at 8x, will first attempt negotiation at 8x. If that attempt
fails, an attempt is made at x4, then a x1 link.Note that the x8 and x4 link widths will
only use the LSB positions from lane 0 while a x1 can be connect to any of the 4
positions (lane0,lane1, lane2, lane3) providing a higher tolerance to single point lane
failures.
PCI Express Port Support Summary
The following table describes the options and limitations supported by the MCH PCI
Express ports.
Number of supported ports
Max payload
Hot-Plug
Virtual Channels
Isochrony
ECRC
Ordering
No Snoop
PEWIDTH[3:0]
others
others
0000
0001
0010
0011
1000
1001
1010
1011
1111
Parameter
Port0
(ESI)
x4.
x4
x4
x4
x4
x4
x4
x4
x4
Port2
The MCH will support six x4 standard PCI Express ports and an additional
x4 ESI port for Intel® 631xESB/632xESB I/O Controller Hub. (Total: 6 +
1 = 7 ports)
256B
Serial port to support pins
MCH only supports VC0
MCH does not support isochrony
MCH does not support ECRC
MCH only supports strict PCI ordering
MCH will not snoop processor caches for transactions with the No Snoop
attribute
x4
x4
x4
x4
x8
x8
x8
x8
All port widths determined by link negotiation.
Port3
x4
x4
x4
x4
Reserved
Reserved
Port4
x4
x4
x4
x4
x8
x8
x8
x8
Support
Port5
x4
x4
x4
x4
Port6
x4
x4
x4
x4
x8
x8
x8
x8
Port7
x4
x4
x4
x4
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