NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 230

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.23.10
230
FBDISTS[1:0][1:0] - FB-DIMM Initialization Status
The contents of this register are valid only during “Initialization” states. The thirteen
bits [12:0] correspond to the northbound bit-lanes.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:13
12:0
6:4
3:0
Bit
Bit
Attr
Attr
RW
RW
RO
RV
21
0
47h, 46h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
47h, 46h
Intel 5000P Chipset
21
0
5Ah, 58h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
5Ah, 58h
Intel 5000P Chipset
Default
Default
0000h
000
00
0h
INITPAT: Initialization pattern
This pattern is superseded by the “EN” bit.
This field is not used during fast reset.
The note ‘(not valid in “Reset”)’ indicates that is not valid when
FBDST.STATE=”Reset” or “Recovery Reset” and EN=’1’. The note ‘(valid only in
“Reset”)’ indicates that this is valid only when FBDST.STATE=”Reset” or
“Recovery Reset”.
AMBID: Advanced Memory Buffer IDentifier
Driven during the training sequences.
This field is also used during fast reset to identify the last (southernmost)
DIMM.
Reserved
PATDET: Pattern Detection
Bit-Lane Status is evaluated at the end of each instance of the pattern
specified by the FBDICMD.EN and FBDICMD.INITPAT fields. Bit-Lane status is
evaluated on each change to the FBDICMD.EN and FBDICMD.INITPAT.Only bits
[2:0] are valid during electrical idle, and only after the FBDRST reset sequence
has been executed.
A recognizable training sequence must contain the FBDICMD.AMBID.
TS1 detection is qualified by test patterns specified in section 4.3 of rev. 0.75
of FBD DFx specification, which defines the “SB/NB_Mapping” (1 bit), the “Test
Parameters” (24 bits), and the “Electrical Stress Pattern”.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
“000”=TS0: Training Sequence 0 to last AMB (not valid in “Reset”)
“001”=TS1: Training Sequence 1 to last AMB (not valid in “Reset”)
“010”=TS2: Training Sequence 2 to last AMB (not valid in “Reset”)
“011”=TS3: Training Sequence 3 to last AMB (not valid in “Reset”)
“100”=reserved
“101”=TS2: Training Sequence 2 not to last AMB with NB Merge disabled
“110”=TS2: Training Sequence 2 not to last AMB with NB Merge enabled
“111”=All Ones (valid only in “Reset”)
“1” = Pattern recognized.
“0” = Pattern not recognized.
(not valid in “Reset”)
(not valid in “Reset”)
Description
Description
Register Description