NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 122

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

122
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Bit
5
4
3
2
1
0
Attr
RW
RW
RW
RW
RW
RO
2-3
0
3Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Eh
Intel 5000Z Chipset
4-7
0
3Eh
Intel 5000P Chipset
Default
0
0
0
0
0
0
MAMODE: Master Abort Mode
Not applicable to PCI Express. This bit is hardwired to 0.
VGA16bdecode: VGA 16-bit decode
This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of
VGA I/O address precluding the decoding of alias addresses every 1 KB. The
I/O addresses decoded is in the range of 03B0h to 03BBh or 03C0h to 03DFh
within the first 1KB I/O space.
0: execute 10-bit address decodes on VGA I/O accesses.
1: execute 16-bit address decodes on VGA I/O accesses.
This bit only has meaning if bit 3 (VGAEN) of this register is also set to 1,
enabling VGA I/O decoding and forwarding by the bridge.
This read/write bit enables system configuration software to select between
10- and 16-bit I/O address decoding for all VGA I/O register accesses that are
forwarded from the primary to secondary whenever the VGAEN is set to 1.
VGAEN: VGA Enable
Controls the routing of CPU initiated transactions targeting VGA compatible I/
O and memory address ranges. This bit may only be set for one PCI Express
port.
ISAEN: ISA Enable
Modifies the response by the
by the CPU that target ISA I/O addresses. This applies only to I/O addresses
that are enabled by the IOBASE and IOLIM registers.
1: The
transactions addressing the last 768 bytes in each 1KB block even if the
addresses are within the range defined by the IOBASE and IOLIM registers.
See
forwarded to ESI where they can be subtractively or positively claimed by the
ISA bridge.
0: All addresses defined by the IOBASE and IOLIM for CPU I/O transactions
will be mapped to PCI Express.
BCSERRE: SERR Enable
This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages from the PCI Express port to the primary side.
1: Enables forwarding of
messages.
0: Disables forwarding of
Note that BCSERRE is no longer a gating item for the recording of the
SESCSTS.SRSE error.
PRSPEN: Parity Error Response Enable
This bit controls the response to poisoned TLPs in the PCI Express port
1: Enables reporting of poisoned TLP errors.
0: Disables reporting of poisoned TLP errors
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Section 4.5.2
Intel 5000P Chipset MCH
. Instead of going to PCI Express these cycles will be
ERR_COR, ERR_NONFATAL and ERR_FATAL
ERR_COR, ERR_NONFATAL and ERR_FATAL.
Intel 5000P Chipset MCH
will not forward to PCI Express any I/O
Description
to an I/O access issued
Register Description