NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 113
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Register Description
3.8.8.15
K
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
SECSTS[7:2] - Secondary Status
SECSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (that is, PCI Express side) of the “virtual” PCI-PCI
bridge embedded within MCH.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
3:0
Bit
Bit
15
14
13
12
RWC
RWC
RWC
RWC
Attr
Attr
RO
2-3
0
1Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Dh
Intel 5000Z Chipset
4-7
0
1Dh
Intel 5000P Chipset
2-3
0
1Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Eh
Intel 5000Z Chipset
4-7
0
1Eh
Intel 5000P Chipset
Default
Default
0h
0
0
0
0
IOLCAP: I/O Address Limit Capability
0h – 16 bit I/O addressing, (supported)
1h – 32 bit I/O addressing,
others - Reserved.
The
0.
SDPE: Detected Parity Error
This bit is set by the
TLP in the PCI Express port regardless of the state the Parity Error Response
bit (in the BCTRL.PRSPEN register).
BCTRL.PRSPEN register). This corresponds to IO4 as defined in
“Intel 5000P Chipset Error List” on page
SRSE: Received System Error
This bit is set by the
message.
for the recording of this error on the secondary side).
SRMAS: Received Master Abort Status
This bit is set when the PCI Express port receives a Completion with
“Unsupported Request Completion” Status.
SRTAS: Received Target Abort Status
This bit is set when the PCI Express port receives a Completion with
“Completer Abort” Status.
MCH
does not support 32 bit I/O addressing, so these bits are hardwired to
Section 3.8.8.28
Intel 5000P Chipset MCH
MCH
when it receives a ERR_FATAL or ERR_NONFATAL
. (Note that BCTRL.BCSERRE is not a gating item
Description
Description
381.
whenever it receives a poisoned
Table 5-31,
113
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