NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 374
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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5.15.9
374
1. This does not include the ESI (port 0) which is not hot-pluggable.
The compatible set of hot-plug registers may be accessed via memory-mapped
transactions, or via the Intel 5000P Chipset MCH configuration mechanism as defined in
the configuration mechanism chapter of this document. For specific information on the
hot-plug register set, refer to the chapter on configuration register details.
The messages used for the hot-plug model are listed in
Plug Interrupt Flow” on page 336
Controller Hub Port Configurations” on page 345
and LEDs.
Virtual Pin Ports
Shown in the
maximum number of PCI Express card slots that could be supported for hot-plug
operations. In this VPP usage model, 16 slots (max) are shown in
Intel 5000P Chipset Platform only 6 PCI Express slots
operations.
Note: Port 0, the ESI slot, is not hot-pluggable.
Since Intel 5000P Chipset MCH has only six PCI Express ports, only six hot-plug slots
should be present in a Intel 5000P Chipset MCH platform. Intel 5000P Chipset MCH PCI
Express virtual pin port will only process six hot-plug slots accordingly.
Figure 5-1
is a high level block diagram of virtual pin ports and theoretical
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
and
Table 5-18, “MCH to Intel 631xESB/632xESB I/O
describe the behavior of the button
1
will be used for the I/O hot-plug
Table 5-14, “PCI Express Hot-
Figure 5-1
Functional Description
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