NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 22
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Introduction
which gives a total read bandwidth of 17 GB/s for four FB-DIMM channels. Thus, this
provides 8.5 GB/s of write memory bandwidth for four FB-DIMM channels. The read
bandwidth for each FB-DIMM channel is 5.3GB/s for DDR2 667FB-DIMM memory which
gives a total read bandwidth of 21 GB/s for four FB-DIMM channels. Thus, this provides
10.7 GB/s of write memory bandwidth for four FB-DIMM channels. The total bandwidth
is based on read bandwidth thus the total bandwidth is 17 GB/s for 533 and 21.0 GB/s
for 667.
The Intel 631xESB/632xESB I/O Controller Hub integrates an Ultra ATA 100 controller,
six Serial ATA host controller ports, one EHCI host controller, and four UHCI host
controllers supporting eight external USB 2.0 ports, LPC interface controller, and a flash
BIOS interface controller. Additionally the Intel 631xESB/632xESB I/O Controller Hub
contains a PCI interface controller, Azalia / AC’97 digital controller, integrated LAN
controller, an ASF controller and a ESI for communication with the MCH. The Intel
631xESB/632xESB I/O Controller Hub component provides the data buffering and
interface arbitration required to ensure that system interfaces operate efficiently and
provide the bandwidth necessary to enable the system to obtain peak performance.
The Intel 631xESB/632xESB I/O Controller Hub elevates Serial ATA storage
performance to the next level with Intel RAID.
The ACPI compliant Intel 631xESB/632xESB I/O Controller Hub platform can support
the Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-Off power
management states. Through the use of the integrated LAN functions, the Intel
631xESB/632xESB I/O Controller Hub also supports Alert Standard Format for remote
management.
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Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
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