NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 114

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 3-33. Intel 5000P Chipset MCH PCISTS and SECSTS Master/Data Parity Error RAS
114
Handling
a. In general, the DPE field is the superset of the MDPERR from a virtual PCI-PCI bridge perspective
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
10:9
4:0
but there may be cases where a PCISTS[8].MDPERR may not be logged in the PCISTS[15].DPE
field in the Intel 5000P Chipset MCH on the primary side.
Bit
11
8
7
6
5
RWC
RWC
Attr
RO
RO
RO
RV
RV
SECSTS[8].SMDPERR
PCISTS[8].MDPERR
2-3
0
1Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Eh
Intel 5000Z Chipset
4-7
0
1Eh
Intel 5000P Chipset
SECSTS[15].SDPE
PCISTS[15].DPE
Register Name
Default
00
0h
0
0
0
0
0
SSTAS: Signaled Target Abort
This bit is set when the PCI Express port completes a request with “Completer
Abort” Status when the PEXSTS.RTA is set since the MCH acts as a virtual
PCI bridge and passes the completion abort from the primary to the secondary
side.
Note however that the MCH will not set the SSTAS field directly on the
secondary side since all requests are passed upstream through the primary
side to the internal core logic for decoding.
SDEVT: DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0
SMDPERR: Master Data Parity Error
This bit is set by the PCI Express port on the secondary side (PCI Express
link) if the Parity Error Response Enable bit (PRSPEN) in the
is set and either of the following two conditions occurs:
•The PCI Express port receives a Completion marked poisoned
•The PCI Express port poisons a write Request
If the Parity Error Response Enable bit is cleared, this bit is never set. Refer to
Table 3-33
Chipset MCH.
SFB2BTC: Fast Back-to-Back Transactions Capable
Not applicable to PCI Express. Hardwired to 0.
Reserved. (by PCI SIG)
S66MHCAP: 66 MHz capability
Not applicable to PCI Express. Hardwired to 0.
Reserved. (by PCI SIG)
a
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
for details on the data parity error handling matrix in the Intel 5000P
OB Post OB Compl
yes
no
no
no
yes
yes
Description
no
no
IN Post
yes
no
no
no
IB Compl
Register Description
yes
yes
no
no
Section 3.8.8.28