NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 370

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 5-40. SMBus Configuration Write (Word Writes, PEC Enabled)
Figure 5-41. SMBus Configuration Write (Write Bytes, PEC Enabled)
5.15.4.4
5.15.4.5
Note:
370
SMBus Error Handling
The SMBus slave interface handles two types of errors: Internal and PEC. For example,
internal errors can occur when the Intel 5000P Chipset issues a configuration read on
the PCI Express port that read’s terminates in error. These errors manifest as a not-
acknowledge (NAK) for the read command (End bit is set). If an internal error occurs
during a configuration write, the final write command receives a NAK just before the
stop bit. If the master receives a NAK, the entire configuration transaction should be
reattempted.
If the master supports Packet Error Checking (PEC) and the PEC_en bit in the command
is set, then the PEC byte is checked in the slave interface. If the check indicates a
failure, then the slave will NAK the PEC packet.
SMBus Interface Reset
Since the configuration registers are affected by the reset pin, SMBus masters will not
be able to access the internal registers while the system is reset.
• The slave interface state machine can be reset by the master in two ways:
• The master holds SCL low for 25 ms cumulative. Cumulative in this case means
• The master holds SCL continuously high for 50 ms.
S
S
S
S
S
S
S
S
S
S
S
S
that all the “low time” for SCL is counted between the Start and Stop bit. If this
totals 25 ms before reaching the Stop bit, the interface is reset.
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
1 1X 0_ X X X
1 1X 0_ X X X
1 1X 0_ X X X
11 X 0_X X X
1 1X 0_ X X X
1 1X 0_ X X X
1 1X 0_ X X X
1 1X 0_ X X X
W A
W A
W A
W A
W A
W A
W A
W A
W A
W A
W A
W A
Cmd = 10011101
Cmd = 00011101
Cmd = 00011101
Cmd = 01011101
C m d = 10 011 100
C m d = 00 011 100
C m d = 00 011 100
C m d = 00 0111 00
C m d = 00 011 100
C m d = 00 011 100
C m d = 00 011 100
C m d = 01 011 100
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
A
A
A
A
Register[15:8]
Bus Number
Data[31:24]
Data[15:8]
A
A
A
A
A
A
A
A
D evice /Fu nction
R e giste r[1 5:8 ]
R e giste r[7 :0]
B u s N u m be r
D a ta[31 :24 ]
D a ta[23 :16 ]
D a ta[1 5:8]
A
A
A
A
D ata[7 :0]
Device/Function
Register[7:0]
Data[23:16]
Data[7:0]
A
A
A
A
A
A
A
A
A
A
A
A
Functional Description
P E C
P E C
P E C
P E C
P E C
P E C
P E C
P E C
PEC
PEC
PEC
PEC
A P
A P
A P
A P
A
A
A
A
A
A
A
A
P
P
P
P
P
P
P
P