NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 81

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.1.5
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
HDR - Header Type Register
This register identifies the header layout of the configuration space.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
6:0
Bit
7
Attr
RO
RO
0, 2-3, 8, 9
0
0Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
0Eh
Intel 5000Z Chipset
4-7
0
0Eh
Intel 5000P Chipset
16
0, 2
0Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
17
0
0Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
21
0
0Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
0Eh
Intel 5000P Chipset
(DEV2-7)
(DEV16)
Default
{01h}
{00h}
{1h}
{0h}
endif
endif
else
else
if
if
Multi-function Device.
Selects whether this is a multi-function device, that may have alternative
configuration layouts. This bit is hardwired to ‘0’ for devices for the MCH with the
exception of device 16 fn 0-2, which it is set to ‘1’.
Configuration Layout.
This field identifies the format of the configuration header layout for a PCI-to-PCI
bridge from bytes 10h through 3Fh.
For PCI Express Devices 2,3,4,5,6,7 default is 01h, indicating
For all other Devices: 0,8,9,16,17,21,22 default is 00h, indicating a conventional
type 00h PCI header
Description
“PCI to PCI Bridge”
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