NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 238

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.25.2
238
FBD[1:0]IBPORTCTL: FB-DIMM IBIST Port Control Register
This register contains bits to control the operation of the IBIST DFT feature.
Device:
Function: 0
Offset:
31:26
21:12
11:8
Bit
25
24
23
22
RWST
RWST
ROST
Attr
RW
RW
RW
21
280h, 180h
RV
Default
000h
00h
0h
0
1
0
0
Reserved
RXINVSWPMD: Rx Inversion Sweep Mode
0: Match Sweep according to the SB-to-NB_Mapping field in the TS1 training
sequence.
The default setting forces the RX inversion pointers to follow the unique
northbound inversion across the port width. It is based on a Modulo 5 of Intel
5000P Chipset MCHMAP bit setting. If e lanes Example;
If Intel 5000P Chipset MCHMAP = 0 then Lanes [4:0] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
If Intel 5000P Chipset MCHMAP = 1 then Lanes [9:5] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
For Intel 5000P Chipset MCH lane [13] does not exist but it does participate in
rotate-left-shift operations.
1: Enable full inversion sweep across the entire port.
When enabled the RX inversion pointers become a single entity.
Lanes [13:10] rotate left-shift completely across the width of the port. Even
though Lane[13] is a DFT lane it will be “shifted through” to make the logic
design easier.
0->1->2->3->4->5->6->7->8->9->10->11->12->13->0.
RXAUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBRXSHFT register.
0: Disable Auto-inversion
1: Enable Auto-inversion
Intel 5000P Chipset MCHMAP: Southbound to northbound mapping for
loopback testing
This bit indicates which set of lanes are replicated onto the northbound lanes.
0: Lower SB lanes
1: Upper SB lanes
CMMSTR: Compliance Measurement Mode
This bit forces the component into link reset then transmits the contents of the
default IBIST pattern set continuously (depending on implementation) on all Tx
lanes until this bit is cleared and the IBSTR bit is cleared. If the IBIST engine is
used for CMM then the standard initialization sequence is follow with TS0, TS1
training set prior to entry into IBIST.
0: Disable CMM
1: Enable CMM. This feature requires the IBIST start bit to be set before the
mode is enabled.
ERRCNT: Error Counter [9:0]
Total number of errors encountered in this port. Errors are accumulated per lane.
If several errors occurred in one phit time then a binary encoded value of the
number of errors is added to the error count.
ERRLNNUM: Error Lane Number [3:0]
This points to the first lane that encountered an error. If more than one lane
reports an error in a cycle, the most significant lane number that reported the
error will be logged.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description