NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 17

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Introduction
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Full Duplex
GART
GB/s
Gb/s
Hardwired
Half Duplex
Host
I/O
ICH6
Intel® 631xESB/
632xESB I/O
Controller Hub
Implicit Writeback
Inband
Inbound
Incoming
Inbound (IB)/
Outbound (OB),
AKA Upstream/
DownStream,
Northbound/
Southbound,
Upbound/
Downbound
Initiator
Isochronous
Layer
Legacy
Line
Link
Lock
LSb
LSB
Master
Master Abort
MB/s
Terminology
A connection or channel that allows data or messages to be transmitted in opposite
directions simultaneously.
Graphics Aperture Remap Table. GART is a table in memory containing the page remap
information used during AGP aperture address translations.
Gigabytes per second (10
Gigabits per second (10
A parameter that has a fixed value.
A connection or channel that allows data or messages to be transmitted in either
direction, but not simultaneously.
This term is used synonymously with processor.
1.
2.
6th Generation I/O controller Hub. The I/O Controller Hub component that contains the
legacy I/O functions. It communicates with the MCH over a proprietary interconnect called
the DMI interface.
6th Generation I/O Controller Hub. The I/O Controller Hub component that contains the
legacy I/O functions.
A snoop initiated data transfer from the bus agent with the modified Cache Line to the
memory controller due to an access to that line.
Communication that is multiplexed on the standard lines of an interface, rather than
requiring a dedicated signal.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound.”
A transaction or data that enters the MCH.
Up, North, or Inbound is in the direction of the processor, Down, South, or Outbound is in
the direction of I/O (SDRAM, SMBus).
The source of requests. An agent sending a request packet on PCI Express is referred to
as the Initiator for that transaction. The Initiator may receive a completion for the
request.
A classification of transactions or a stream of transactions that require service within a
fixed time interval.
A level of abstraction commonly used in interface specifications as a tool to group
elements related to a basic function of the interface within a layer and to identify key
interactions between layers.
Functional requirements handed down from previous chipsets or PC compatibility
requirements from the past.
Cache line.
The layer of an interface that handles flow control and often error correction by retry.
A sequence of transactions that must be completed atomically.
Least Significant Bit
Least Significant Byte
A device or logical entity that is capable of initiating transactions. A Master is any potential
Initiator.
A response to an illegal request. Reads receive all ones. Writes have no effect.
Megabytes per second (10
Input/Output.
When used as a qualifier to a transaction type, specifies that transaction targets Intel
architecture-specific I/O space. (e.g., I/O read)
9
bits per second).
9
6
bytes per second).
bytes per second)
Description
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