NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 227

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.9.23.6
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
SPCPS[1:0] - Spare Copy Status
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:4
3:1
7:6
3:1
Bit
Bit
0
5
4
0
Attr
RWL
Attr
RW
RW
RO
RO
RO
RO
RV
21
0
40h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
40h
Intel 5000P Chipset
21
0
41h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
41h
Intel 5000P Chipset
Default
Default
000
00
0h
0h
0
0
0
0
SETH: Spare Error Threshold
A spare fail-over operation will commence when the SPAREN bit is set and a
UERRCNT.RANK[i] and/or CERRCNT.RANK[i] count for one and only one rank hits
this threshold.
SPRANK: Spare Rank
Target of the spare copy operation. This rank should not initially appear in a
DMIR.RANK field. After the spare copy, Intel 5000P Chipset MCH will update the
failed DMIR.RANK fields with this value. Enabled by SPAREN. Changes to this
register will not be acknowledged by the hardware while SPCPS.DSCIP is set.
SPAREN: Spare Control Enable
‘1’ enables sparing, ‘0’ disables sparing. The SPRANK field defines other
characteristics of the sparing operation. The Intel 5000P Chipset MCH does not
support sparing in mirrored mode: this bit should not be set if MC.MIRROR is set.
If this bit is cleared before SPCPS.SFO is set, then if this bit is subsequently set
while the spare trigger is still valid, then the spare copy operation will not resume
from where it left off, but will instead restart from the beginning.
Reserved
LBTHR: Leaky Bucket Threshold Reached
‘0’ = Leaky-bucket threshold not reached
‘1’ = Leaky-bucket count matches SPCPC.SETH. Generates error M27. Cleared by
reducing the offending count(s) in the UERRCNT/CERRCNT registers.
DSCIP: DIMM Sparing Copy In Progress
‘0’ = DIMM sparing copy not in progress.
‘1’ = DIMM sparing copy in progress. Set when SPCPC.SPAREN is set, and only one
rank in UERRCNT/CERRCNT is at threshold. This bit remains set until SFO is set.
This bit is cleared when SFO is set. Error M27 is set when this bit transitions from
‘0’ to ‘1’.
FR: Failed Rank
Rank that was spared. Updated with the UERRCNT/CERRCNT rank that has reached
threshold when DSCIP is set.
SFO: Spare Fail-Over
‘0’ = Spare has not been substituted for failing DIMM rank.
‘1’ = Spare has been substituted for failing DIMM rank. Generates error M28.
Cleared when SPCPC.SPAREN is cleared.
Description
Description
227