NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 363

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.15.2.4
5.15.2.5
5.15.2.6
5.15.2.7
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Address Byte 2 Field
This field indicates the Device Number and Function Number of the desired
configuration register if for a configuration type access, otherwise it should be set
to zero.
Address Byte 1 Field
This field indicates the upper address bits for the 4K region specified by the
register offset. Only the lower bit positions of this field are used, the upper four bits
are ignored.
Address Byte 0 Field
This field indicates the lower eight address bits for the register with the 4K region,
regardless whether it is a configuration or memory-map type of access.
Data Field
This field is used to receive read data or to provide write data associated with the
addressed register.
At the completion of a read command, this field will contain the data retrieved from the
addressed register. All reads will return an entire aligned DWord (32 bits) of data.
For write operations, the number of byte(s) of this 32 bit field is loaded with the desired
write data. For a byte write only bits 7:0 will be used, for a Word write only bits 15:0
will be used, and for a DWord write all 32 bits will be used.
Position
Position
Position
Position
Position
23:16
31:24
15:8
2:0
3:0
7:0
7:3
7:4
7:0
4:0
7:5
Device Number. Can only be devices on the MCH.
Function Number.
Ignored.
Extended Register Number. Upper address bits for the 4K region of register offset.
Register Offset.
Byte 3 (DATA3). Data bits [31:24] for DWord.
Byte 2 (DATA2). Data bits [23:16] for DWord.
Byte 1 (DATA1). Data bits [15:8] for DWord and Word.
Byte 0 (DATA0). Data bits [7:0] for DWord, Word and Byte.
Ignored.
Bus Number. Must be zero: the SMBus port
can only access devices on the MCH and all
devices are bus zero.
Configuration Register Mode Description
Configuration Register Mode Description
Description
Description
Description
Memory map region to access.
01h = DMA
08h = DDR
09h = CHAP
Others = Reserved
Zeros used for padding.
Memory Mapped Mode Description
Memory Mapped Mode Description
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