NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 201

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Register Description
Table 3-41. FB-DIMM Host Data Cycle Valid Mux Select
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
a. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
b. Ignored by Mgr registers in the 5:4 mode.
Notes:
FSB:Memory Frequency
respective memory gearing registers (no mix and match).
333:333
267:267
400:400
333:267
267:333
267:333
4:5 (conservative)
4:5 (aggressive)
Gear Ratio
1:1
5:4
a
Value
00h
00h
01h
04h
b
201

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