NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 112

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.8.14
112
Only the upper 4 bits are programmable. For the purpose of address decode, address
bits A[11:0] are treated as 0. The bottom of the defined I/O address range will be
aligned to a 4 KB boundary while the top of the region specified by IO_LIMIT will be one
less than a 4 KB multiple. Refer to
Chipset Platform Specification.
IOLIM[7:2] - I/O Limit Register
The I/O Base and I/O Limit registers define an address range that is used by the PCI
Express bridge to determine when to forward I/O transactions from one interface to the
other using the following formula:
Only the upper 4 bits of this register are programmable. For the purpose of address
decode, address bits A[11:0] of the I/O limit register is treated as FFFh.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:4
3:0
7:4
Bit
Bit
Attr
Attr
RW
RW
RO
2-3
0
1Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Ch
Intel 5000Z Chipset
4-7
0
1Ch
Intel 5000P Chipset
2-3
0
1Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Dh
Intel 5000Z Chipset
4-7
0
1Dh
Intel 5000P Chipset
Default
Default
0h
0h
0h
IO_BASE <= A[15:12] <=IO_LIMIT
IOBASE: I/O Base Address
Corresponds to A[15:12] of the I/O addresses at the PCI Express port.
IOCAP: I/O Address capability
0h – 16 bit I/O addressing, (supported)
1h – 32 bit I/O addressing,
Others - Reserved.
The
IOLIMIT: I/O Address Limit
Corresponds to A[15:12] of the I/O addresses at the PCI Express port.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
MCH
does not support 32 bit addressing, so these bits are hardwired to 0.
Section 4.5.1
and
Description
Description
Section 4.5.3
in the Intel 5000P
Register Description