NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 402

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 8-1.
8.1.3
406
Simplified TAP Controller Block Diagram
The TAP logic consists of a finite state machine controller, a serially-accessible
instruction register, instruction decode logic and data registers. The set of data
registers includes those described in the 1149.1 standard (the bypass register, device
ID register, and so forth.), plus Intel 5000P Chipset specific additions.
Accessing the TAP Logic
The TAP is accessed through an 1149.1-compliant TAP controller finite state machine,
which is illustrated in
the TAP Instruction Register or to one of the component-specific data registers. The
TMS pin controls the progress through the state machine. TAP instructions and test
data are loaded serially (in the Shift-IR and Shift-DR states, respectively) using the TDI
pin. A brief description of the controller’s states follows; refer to the IEEE 1149.1
standard for more detailed descriptions.
Figure
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
8-1. The two major branches represent access to either
Testability