NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 373

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.15.6.1
5.15.6.2
5.15.7
5.15.8
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
A standard hot-plug usage model is beneficial to customers who buy systems with hot-
plug slots because many customers utilize hardware and software from different
vendors. A standard usage model allows customers to use the PCI hot-plug slots on all
of their systems without having to retrain operators.
In order to define a programming model for the PCI Standard Hot-Plug Controller
(SHPC), it is necessary to make some assumptions about the interface between a
human operator and a hot-plug slot. The SHPC programming model includes two
indicators, one optional push button, and a sensor on the manually-operated retention
latch for each supported slot.
Hot-Plug Indicators
The Standard Usage Model assumes that the platform provides two indicators per slot
(the Power Indicator and the Attention Indicator). Each indicator is in one of three
states: on, off, or blinking. Hot-plug system software has exclusive control of the
indicator states by issuing commands to the SHPC.
The SHPC controls blink frequency, duty cycle, and phase. Blinking indicators operate
at a frequency of 1.5 Hz and 50% (+/- 5%) duty cycle. Both indicators are completely
under the control of system software.
Attention Button
An Attention Button is a momentary-contact push-button, located adjacent to each
hotplug slot, that is pressed by the user to initiate a hot-insertion or a hot-removal at
that slot. The Power Indicator provides visual feedback to the human operator (if the
system software accepts the request initiated by the Attention Button) by blinking.
Once the Power Indicator begins blinking, a 5-second abort interval exists during which
a second depression of the Attention Button cancels the operation. Software has the
responsibility to implement this 5-second abort interval.
Hot-Plug Controller
PCI Express Hot-Plug requires that the Intel 5000P Chipset MCH implement a Hot-Plug
controller for every Hot-Pluggable interface. The Hot-Plug controller is a capability of
the bridge configuration space and the register set is accessible through the standard
PCI capability mechanism defined in the PCI Express Base Specification, Revision 1.0a.
Details on Hot-Plug operation and flow will be described in the Intel 5000P Chipset
Software Programmer’s Guide.
PCI Express Hot-Plug Usage Model
Not all concepts from the PCI standard hot-plug definition apply directly to PCI Express
interfaces. The PCI Express specification still calls for an identical software interface in
order to facilitate adoption with minimal development overhead on this aspect of the
implementation. The largest variance from the old PCI hot-plug model is in control of
the interface itself. PCI required arbitration support for idling already connected
components, and “quick switches” to isolate the bus interface pins of a hot-plug slot.
PCI Express is a point-to-point interface, making hot-plug a degenerate case of the old
model that doesn’t require such arbiter support. Furthermore, the PCI Express
interface is inherently tolerant of hot connect or disconnect, and does not have explicit
clock or reset pins defined as a part of the bus (although they are standard pieces of
some defined PCI Express connector form factors). As a result of these differences,
some of the inherited hot-plug command and status codes are misleading when applied
to PCI Express.
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