NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 46

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.2
46
Platform Configuration Structure
In some previous chipsets, the MCH and the South Bridge were physically connected by
PCI bus 0. From a configuration standpoint, both components appeared to be on PCI
bus 0 which was also the system’s primary PCI expansion bus. The MCH contained two
PCI devices while the south bridge was considered one PCI device with multiple
functions.
In the Intel 5000P platform, the configuration structure is significantly different. The
MCH and the Intel 631xESB/632xESB I/O Controller Hub are physically connected by
the ESI interface; thus, from a configuration standpoint, the ESI interface is logically
PCI bus 0. As a result, all devices internal to the MCH and Intel 631xESB/632xESB I/O
Controller Hub appear to be on PCI bus 0. The system’s primary PCI expansion bus is
physically attached to the Intel 631xESB/632xESB I/O Controller Hub and, from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI
bridge; therefore, it has a programmable PCI Bus number.
RWS
RWL
RWO
RRW
L
RV
Reserved Bits
Reserved
Registers
Default Value
upon a Reset
the end of a bit
name
“ST” appended to
Term
Read/Write/Set: A register bit can be either read or set by software. In order to set
this bit, a one must be written to it. Writing a zero to this bit has no effect. Hardware will
clear this bit.
Read/Write/Lock. A register bit with this attribute can be read or written by software.
Hardware or a configuration bit can lock bit and prevent it from updated.
Read/Write Once. A register bit with this attribute can be written to only once after
power up. After the first write, the bit becomes read only. This attribute is applied on a bit
by bit basis. For example, if the RWO attribute is applied to a 2 bit field, and only one bit
is written, then the written bit cannot be rewritten (unless reset). The unwritten bit, of
the field, may still be written once. This is special case of RWL.
Read/Restricted Write. This bit can be read and written by software. However, only
supported values will be written. Writes of non supported values will have no effect.
Lock. A register bit with this attribute becomes Read Only after a lock bit is set.
Reserved Bit. This bit is reserved for future expansion and must not be written. The PCI
Local Bus Specification, Revision 2.2 requires that reserved bits must be preserved. Any
software that modifies a register that contains a reserved bit is responsible for reading
the register, modifying the desired bits, and writing back the result.
Some of the MCH registers described in this section contain reserved bits. These bits are
labeled “Reserved”. Software must deal correctly with fields that are reserved. On reads,
software must use appropriate masks to extract the defined bits and not rely on reserved
bits being any particular value. On writes, software must ensure that the values of
reserved bit positions are preserved. That is, the values of reserved bit positions must
first be read, merged with the new values for other bit positions and then written back.
Note that software does not need to perform a read-merge-write operation for the
Configuration Address (CONFIG_ADDRESS) register.
In addition to reserved bits within a register, the MCH contains address locations in the
configuration space of the Host-ESI bridge entity that are marked either “Reserved” or
“Intel Reserved”. The MCH responds to accesses to “Reserved” address locations by
completing the host cycle. When a “Reserved” register location is read, a zero value is
returned. (“Reserved” registers can be 8, 16, or 32 bits in size). Writes to “Reserved”
registers have no effect on the MCH. Registers that are marked as “Intel Reserved” must
not be modified by system software. Writes to “Intel Reserved” registers may cause
system failure. Reads to “Intel Reserved” registers may return a non-zero value.
Upon a reset, the MCH sets all of its internal configuration registers to predetermined
default states. Some register values at reset are determined by external strapping
options. The default state represents the minimum functionality feature set required to
successfully bring up the system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization software (usually BIOS)
to properly determine the DRAM configurations, operating parameters and optional
system features that are applicable, and to program the MCH registers accordingly.
The bit is “sticky” or unchanged by a hard reset. These bits can only be cleared by a
PWRGOOD reset.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description