NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 345

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Figure 5-18. MCH to Intel 631xESB/632xESB I/O Controller Hub Port Configurations
5.12.4
Figure 5-19. Intel 5000P Chipset PCI Express General Purpose Ports
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PCI Express General Purpose Ports
Port 4, Port 5, Port 6, and Port 7 are configurable for general purpose I/O applications.
These ports are used as general purpose interfaces. Ports 4 and 5 are combinable to
form a single x8 port. Ports 6 and 7 are combinable to form a single x8 port. When
combining ports the controlling ports registers default to the lower port numbers
address space. Thus when ports 4 and 5 are combined, the control registers are
associated with port 4. These ports are depicted in
P o rt 4
P C I-E x p re s s c lu s te r (IO U 1 )
T ra n s a c tio n
P o rt 5
P h y s ic a l
L in k
P C I- E x4
2 G B/ s e c
I n t e l ® 6 3 1 x E S B / 6 3 2 x E S B I / O C o n t r o l l e r
H u b
P o rt 6
P o r t 3
P C I- E x4
2 G B/ s e c
P o rt 7
M C H
P o r t 2
Figure
2 G B/ s e c
5-19.
E S I
E S I
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