NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 202

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.14
Table 3-42. FB-DIMM to Host Flow Control Mux Select
3.9.15
.
Table 3-43. FB-DIMM Bubble Mux Select
202
GRHOSTFULLCFG: Host Full Flow Control Configuration
This register configures flow control when the host is full. It primarily effects the
Southbound data path and determines when the flow control signal to the core is
asserted.
a. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
GRBUBBLECFG: FB-DIMM Host Bubble Configuration
This register provides valid signals to assert data in the FB-DIMM side for various
gearing ratios. This primarily affects the Northbound data path for the 5:4 configuration
and determines when a bubble is inserted when gearing up.
a. Ignored by Mgr registers in 4:5 mode.
Notes:
Notes:
Device:
Function:
Offset:
Device:
Function:
Offset:
Version:
FSB:Memory Frequency
FSB:Memory Frequency
7:0
respective memory gearing registers (no mix and match).
7:0
Bit
Bit
RWST
333:333
267:267
400:400
333:267
267:333
267:333
RWST
333:333
267:267
400:400
333:267
267:333
Attr
Attr
16
1
16Dh
16
1
16Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
0h
0h
FCMUX: Flow Control Mux Selector
Configures Flow control on the host according to
affect the 5:4 gearing ratio.
FBDBBLMUX: FB-DIMM Data Bubble Mux selector.
Configures bubbles in the host according to
the 5:4 gearing ratio.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
4:5 (conservative)
4:5 (aggressive)
Gear Ratio
Gear Ratio
1:1
5:4
1:1
5:4
4:5
a
Description
Description
Value
Value
00h
00h
02h
02h
08h
00h
04h
Table
a
Table
3-43. This primarily affect
Register Description
3-42. This primarily