NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 92

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.3
3.8.3.1
92
AMB Memory Mapped Registers
The MCH supports four FB-DIMM channels. The MCH supports up to 16 FB-DIMM (each
with its Advanced Memory Buffer [AMB]) on four channels. Software needs to program
AMBPRESENT for each AMB on the platform. There are up to eight functions per AMB
component with 256 B of register space per function.
Intel 5000V Chipset supports only 2 FB-DIMM channels. For more information on the
Intel 5000V Chipset differences see
The MCH supports memory mapped register regions for software to access individual
AMB configuration registers. Memory mapped access to AMB register regions are
converted by the MCH to FB-DIMM channel command encodings subject to
AMBPRESENT register settings (see
programming the AMBASE register. Software is required to program the AMR for the
size of AMB register regions. The size of this region is 128KB. It is mapped to each AMB
addressing slot in 2 KB blocks. If the corresponding AMBPRESENT bit is not set, then
MCH will not send configuration transaction to that AMB addressing slot.
To support SMBus and JTAG access using traditional PCI configuration mechanism, MCH
provides a “switching window” using a dedicated PCI device/function and AMBSELECT
register. AMBSELECT register can be programmed to select an AMB. Bus 0, device 9,
function 0 is mapped to the selected AMB’s configuration registers.
Access to bus 0, device 9, function 0 is limited to SMBus and JTAG only, FSB access to
this function will be mastered aborted by MCH as non-existent PCI function. AMB
register spaces are accessible through the SMBus by the programming of the
AMBSELECT Function_Select field. This field is used select one of the AMB 8
register spaces.
AMBASE: AMB Memory Mapped Register Region Base Register
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
63:40
23:12
Bit
11:0
Bit
RV
Attr
Attr
RW
RV
16
0
64h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
48h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
0h
Default
001h
Default
0h
HECBASE: PCI Express Extended Configuration Base
This register contains the address that corresponds to bits 39 to 28 of the base
address for PCI Express extended configuration space. Configuration software
will read this register to determine where the 256MB range of addresses
resides for this particular host bridge. This register defaults to the same
address as the default value for TOLM.
Reserved
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Reserved
Section
Chapter 7, “Intel® 5000V Chipset Differences.”
3.9.23.11). This region is relocatable by
Description
Description
Register Description