NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 262

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 3-50. IV Vector Table for DMA Errors and Interrupts
3.10.14
3.10.15
262
a. The term “xxxxxx” in the Interrupt vector denotes that software/BIOS initializes them
PEXCAPID: PCI Express Capability ID Register
PEXNPTR: PCI Express Next Pointer Register
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:0
Device:
Function:
Offset:
Version:
7:0
7:0
Bit
Bit
Bit
Number of Messages
and the MCH will not modify any of the “x” bits since it handles only 1 message vector
that is common to all events
enabled by Software
RO
RO
(MMEN)
Attr
Attr
Attr
RW
1
8
0
60h
Intel 5000P Chipset
8
0
6Ch
Intel 5000P Chipset
8
0
6Dh
Intel 5000P Chipset
10h
00h
Default
Default
Default
0h
IV: Interrupt Vector
The interrupt vector as programmed by BIOS/Software will be used by the Intel
5000P Chipset MCH to provide context sensitive interrupt information for different
events such as DMA Errors, DMA completions that require attention from the
processor. See
CAPID:
This code denotes the standard PCI Express capability.
NXTPTR:
The PCI Express capability structure is the last capability in the linked list and set to
NULL.
(DMA completions/errors)
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PCI Express Capability ID
PCI Express Next Pointer
Events
Table 3-50
All
for IV handling for DMA.
Description
Description
Description
xxxxxxxx
IV[7:0]
a
Register Description