NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 404

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

8.1.4
Table 8-2.
8.1.5
8.1.6
408
Shift-DR: The Data Register connected between TDI and TDO as a result of selection by
the current instruction is shifted one stage toward its serial output on each rising edge
of TCK. The output arrives at TDO on the falling edge of TCK. The parallel, latched
output of the selected Data Register does not change while new data is being shifted in.
Pause-DR: Allows shifting of the selected Data Register to be temporarily halted
without stopping TCK. All registers retain their previous values.
Update-DR: Data from the shift register path is loaded into the latched parallel
outputs of the selected Data Register (if applicable) on the falling edge of TCK. This and
Test-Logic-Reset are the only controller states in which the latched paralleled outputs of
a data register can change.
All other states are temporary controller states, used to advance the controller between
active states. During such temporary states, all test registers retain their prior values.
Reset Behavior of the TAP
The TAP and its related hardware are reset by transitioning the TAP controller finite
state machine into the Test-Logic-Reset state. Once in this state, all of the reset actions
listed in
resetting the TAP, the device will function as though the TAP did not exist).
TAP Reset Actions
The TAP can be transitioned to the Test-Logic-Reset state in one of two ways:
Cycling power on a device does not ensure that the TAP is reset. System designers
must utilize one of the two methods stated above to reset the TAP. The method used
depends on the manufacturing and debug requirements of the system.
Clocking the TAP
There is no minimum frequency at which the Intel 5000P Chipset TAP will operate.
Because the private chains are synchronized to the local core clock of that chain there
is a maximum rate relative to the core that the interface can operate. The ratio is 12:1
providing a maximum rate of 27 MHz for a core frequency of 333 MHz.
Accessing the Instruction Register
Figure 8-3
register. This register consists of a 7-bit shift register (connected between TDI and
TDO), and the actual instruction register (which is loaded in parallel from the shift
register). The parallel output of the TAP instruction register goes to the TAP instruction
decoder.
TAP instruction register
Boundary scan logic
TDO pin
• Assert the TRST# pin at any time. This asynchronously resets the TAP controller.
TAP Logic Affected
Figure 8-2
shows the (simplified) physical implementation of the TAP instruction
are performed. The TAP is completely disabled upon reset (i.e. by
TAP Reset State Action
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Tri-stated
Disabled
IDCODE
(instr equivalent to reset is highlighted)
Related TAP Instructions
EXTEST
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Testability