NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 296

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.7.2
Figure 4-5.
4.8
296
Outbound I/O Access
The Intel 5000P Chipset allows I/O addresses to be mapped to resources supported on
the I/O buses underneath the MCH. This I/O space is partitioned into 16 4 KB
segments. Each of the I/O buses can have from 1 to 15 segments mapped to it by
programming its IOBASE and IOLIM registers. Each PCI bus must be assigned
contiguous segments. The lowest segment, from 0 to 0FFFh, is sent to the ESI.
System I/O Address Space
Configuration Space
All chipset registers are represented in the memory address map. In addition, some
registers are also mapped as PCI registers in PCI configuration space.These adhere to
the PCI Local Bus Specification, Revision 2.2.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
1 0003h
FFFFh
F000h
2000h
1000h
0000h
Compatability
(Decoded as
Segment F
Segment E
Segment 2
Segment 1
Segment 0
§
Bus Only
+3 bytes
0 000Xh)
through
System Address Map