NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 199

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
Table 3-38. FB-DIMM to Host Gear Ratio Mux
3.9.11
Table 3-39. FB-DIMM to Host Gear Ratio Mux
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
a. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
FBDTOHOSTGRCFG1: FB-DIMM to Host Gear Ratio
Configuration 1
This register consists of eight nibbles of mux select data for the proper selection of
gearing behavior on the FB-DIMM for the 1:1 and 4:5 modes.This is the second register
for FB-DIMM to Host gearing control.
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:0
31:0
FSB:Memory Frequency
FSB:Memory Frequency
respective memory gearing registers (no mix and match).
Bit
Bit
RWST
333:333
267:267
400:400
333:267
267:333
267:333
RWST
333:333
267:267
400:400
333:267
267:333
267:333
Attr
Attr
16
1
160h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
1
164h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
11111111h
00000000h
Default
Default
FBDHSTGRMUX: FB-DIMM to Host Clock Gearing mux selector.
Eight nibbles of mux select for memory/DDR2 to FSB/core geared clock
boundary crossing phase enables.
Refer to
FBDHSTGRMUX: FB-DIMM to Host Clock Gearing mux selector.
Eight nibbles of mux select for memory/DDR2 to FSB/core geared clock
boundary crossing phase enables.
Refer to
4:5 (conservative)
4:5 (conservative)
4:5 (aggressive)
4:5 (aggressive)
Gear Ratio
Gear Ratio
Table 3-38
Table 3-39
1:1
5:4
1:1
5:4
a
a
for the programming details.
for the programming details.
Description
Description
00000000h
11111111h
00023230h
00004323h
00002323h
00000000h
00002000h
00000400h
Value
Value
b
199