NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 324

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.2.12.10
5.2.12.11
5.2.12.12
324
General Software Usage Assumptions
Under normal circumstances, it is expected that there is no change of throttling values
once it is configured by BIOS during boot. The external Fan control and the BIOS
settings of the OEM via BMC would ensure adequate cooling and maintain the DIMMs
within the prescribed tolerance limits of the TDP. However, situations such as thermal
virus or fan fail down condition might warrant the BIOS/SW to take preemptive action
in adjusting the throttling to say 40-70% of the normal mode before it is cleared. This
means that changes to throttling registers can happen at random intervals (infrequent)
and the platform should be able to tolerate any transients changes that may result
when the Intel 5000P Chipset is updated with the new throttle values. These
requirements are captured below.
Dynamic Change Operation Requirements for Open Loop Thermal
Thottling (OLTT)
The Intel 5000P Chipset Memory throttle control register affected by OLTT include
THRTMID (T2), THRTLOW (T1), GBLACT, and the THRTCTRL.THRMHUNT field.
(THRMHUNT=0 selects the open loop mode).
Each update to the above mentioned throttle register takes approximately 40 core
clocks in the configuration ring to complete.
Configuration register updates for throttling should be spaced out at approximately 80
core cycles apart. (2x guard band)
Only one CFC/CF8 or MMCFG configuration transaction is allowed at a time in the
system.
When the number of activates exceed the GBLACT.GBLACTLM in a global throttling
window, OLTT is entered and GBLTHRT is set by the Intel 5000P Chipset for 16
consecutive global throttling windows (irrespective of the new parameters) as
described in
software assigns new values to THRTLOW or THRMID values at some point in time, the
MC cluster will update the registers and use the new values for limiting the activates
immediately via THRMTHRT register for 16 consecutive global throttling windows. See
also
Software can update the throttling registers as frequently as it desires provided it
maintains the minimum spacing for the configuration writes and follows the other
guidelines as described above. It is also software’s responsibility for the fallout/
transient effect of the thermal control algorithm during such updates.
Dynamic Change Operation Requirements for Closed Loop Thermal
Thottling (CLTT)
In addition to all the conditions/requirements as stipulated in
closed loop throttling which uses GB temperature feedback to adjust the throttling
levels requires the following:
• Intel 5000P Chipset Registers that are affected by dynamic updated include
• •When Temperature crosses T
THRTMID (T2), THRTLOW (T1), THRTHI and THRTCTRL.THRMHUNT. (THRMHUNT=1
selects the closed loop mode)
(if THRMCTRL.THRTMODE=0) or the single step function (THRMCTRL.THRMODE=1)
as depicted in the right side of
NOT history-based algorithm except in the staircase mode which uses the old
value. In this case, the staircase function that always decrements the old value of
Figure
5-12.
Section
5.2.12.7. Note that OLTT is NOT history-based algorithm. Hence if
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
mid
Figure
, the CLTT switched to either the staircase function
5-10. See also
Figure
Section
5-12.
Functional Description
Note that CLTT is
5.2.12.11, the