NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 27

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.1
2.1.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Processor Front Side Bus Signals
Processor Front Side Bus 0
FSB0A[35:3]#
FSB0ADS#
FSB0ADSTB[1:0]#
FSB0AP[1:0]#
FSB0BINIT#
FSB0BNR#
FSB0BPM[5:4]
FSB0BPRI#
FSB0BREQ[1:0]#
FSB0D[63:0]#
FSB0DBI[3:0]#
FSB0DBSY#
FSB0DEFER#
Signal Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
O
Type
Processor 0 Address Bus: FSB0A[35:3]# connect to the processor address
bus. During processor cycles, FSB0A[35:3]# are inputs. The MCH drives
FSB0A[35:3]# during snoop cycles on behalf of ESI and AGP/Secondary PCI
initiators. FSB0A[35:3]# are transferred at 2X rate. Note that the address is
inverted on the processor bus.
The MCH drives the FSB0A7# signal, which is then sampled by the processor
and the MCH on the active-to-inactive transition of FSB0RESET#. The
minimum setup time for this signal is 4 FSB0CLKs. The minimum hold time is
2 clocks and the maximum hold time is 20 FSB0CLKs.
Processor 0 Address Strobe: The processor bus owner asserts FSB0ADS#
to indicate the first of two cycles of a request phase. The MCH can assert this
signal for snoop cycles and interrupt messages.
Processor 0 Address Strobe: FSB0ADSTB[1:0]# are source synchronous
strobes used to transfer FSB0A[35:3]# and FSB0REQ[4:0]# at the 2X
transfer rate.
Processor 0 Address Parity: FSB0AP[1:0]# provide parity protection on
the address bus.
Processor 0 Bus Initialization: This signal causes a reset of the bus state
machines.
Processor 0 Block Next Request: This signal is used to block the current
request bus owner from issuing a new request. This signal is used to
dynamically control the processor bus pipeline depth.
Breakpoint /Debug Bus: These signals are breakpoint and performance
monitor signals. These are output from the processor to indicate the status
of breakpoints and programmable counters used for monitoring processor
performance.
Processor 0 Priority Agent Bus Request: The MCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain ownership of the
address bus. This signal has priority over symmetric bus requests and cause
the current symmetric owner to stop issuing new transactions unless the
FSB0LOCK# signal was asserted.
Processor 0 Bus Requests: The MCH pulls the FSB0BREQ0# signal low
during RESET#. The signal is sampled by the processor on the active-to-
inactive transition of FSB0RESET#. The minimum setup time for this signal is
4 FSB0CLKs. The minimum hold time is 2 clocks and the maximum hold time
is 20 FSB0CLKs.
Processor 0 Data Bus: These signals are connected to the processor data
bus. Data on FSB0D[63:0]# is transferred at a 4X rate. Note that the data
signals may be inverted on the processor bus, depending on the P0DBI[3:0]
signals.
Processor 0 Dynamic Bus Inversion: These signals are driven along with
the FSB0D[63:0]# signals. They indicate if the associated signals are
inverted. FSB0DBI[3:0]# are asserted such that the number of data bits
driven electrically low (low voFSB0ltage) within the corresponding 16-bit
group never exceeds 8.
Processor 0 Data Bus Busy: This signal is used by the data bus owner to
hold the data bus for transfers requiring more than one cycle.
Processor 0 Data Bus Defer: Defer indicates that the MCH will terminate
the transaction currently being snooped with either a deferred response or
with a retry response.
StrobeAddress Bits
FSB0ADSTB0#FSB0A[16:3]#, FSB0REQ[4:0]#
FSB0ADSTB1#FSB0A[35:17]#
FSB0DBI[x]#Data Bits
FSB0DBI3#FSB0D[63:48]#
FSB0DBI2#FSB0D[47:32]#
FSB0DBI1#FSB0D[31:16]#
FSB0DBI0#FSB0D[15:0]#
Description
27