NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 361

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.15.2
Table 5-20. SMBus Transaction Field Summary
5.15.2.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
tables, which display this information. Note that the filler byte is not utilized, but
enforces that both types of accesses have the same number of address bytes, and does
allow for future expansion.
It is perfectly legal for an SMBus access to be requested while an FSB-initiated access
is already in progress. The MCH supports “wait your turn” arbitration to resolve all
collisions and overlaps, such that the access that reaches the configuration ring arbiter
first will be serviced first while the conflicting access is held off. An absolute tie at the
arbiter will be resolved in favor of the FSB. Note that SMBus accesses must be allowed
to proceed even if the internal MCH transaction handling hardware and one or more of
the other external MCH interfaces are hung or otherwise unresponsive.
SMBus Transaction Field Definitions
The SMBus target port has it’s own set of fields which the MCH sets when receiving an
SMBus transaction. They are not directly accessible by any means for any device.
Table 5-20
byte address of the MCH itself. Note that the fields can take on different meanings
depending on whether it is a configuration or memory-mapped access type. The
command indicates how to interpret the bytes.
Command Field
The command field indicates the type and size of transfer. All configuration accesses
from the SMBus port are initiated by this field. While a command is in progress, all
future writes or reads will be negative acknowledged (NAK) by the MCH to avoid having
registers overwritten while in use. The two command size fields allows more flexibility
on how the data payload is transferred, both internally and externally. The begin and
end bits support the breaking of the transaction up into smaller transfers, by defining
the start and finish of an overall transfer.
Position
10
11
1
2
3
4
5
6
7
8
9
Mnemonic
indicates the sequence of data as it is presented on the SMBus following the
BYTCNT
ADDR3
ADDR2
ADDR1
ADDR0
DATA3
DATA2
DATA1
DATA0
CMD
STS
Command
Byte Count
Bus Number (Register Mode) or Destination Memory (Memory Mapped Mode)
Device / Function Number (Register Mode) or Address Offset [23:16] (Memory
Mapped Mode)
Extended Register Number (Register Mode) or Address Offset [15:8] (Memory
Mapped Mode)
Register Number (Register Mode) or Address Offset [7:0] (Memory Mapped Mode)
Fourth Data Byte [31:24]
Third Data Byte [23:16]
Second Data Byte [15:8]
First Data Byte [7:0]
Status, only for reads
Field Name
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