NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 327

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Note:
5.4
5.5
5.5.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
An all 0 frame fits this case of good CRC and ECC. This is just as unlikely as any other
random frame contents when interpreting EI.
Interrupts
The Intel 5000P Chipset supports both the XAPIC and traditional 8259 methods of
interrupt delivery. I/O interrupts and inter processor interrupts (IPIs) appear as write
or interrupt transactions in the system and are delivered to the target processor via the
processor bus. This chipset does not support the three-wire sideband bus (the APIC
bus) that is used by Pentium
XAPIC interrupts that are generated from I/O will need to go through an I/O(x)APIC
device unless they support Message Signalled Interrupts (MSI). In this document, I/
O(x)APIC is an interrupt controller that is found in the Intel 631xESB/632xESB I/O
Controller Hub component of the chipset.
The legacy 8259 functionality is embedded in the Intel 631xESB/632xESB I/O
Controller Hub component. The Intel 5000P Chipset will support inband 8259 interrupt
messages from PCI Express devices for boot. The chipset also supports the processor
generated “interrupt acknowledge” (for legacy 8259 interrupts), and “end-of-interrupt”
transactions (XAPIC).
Routing and delivery of interrupt messages and special transactions are described in
this section.
XAPIC Interrupt Message Delivery
The XAPIC interrupt architectures deliver interrupts to the target processor core via
interrupt messages presented on the front side bus. This section describes how
messages are routed and delivered in a Intel 5000P Chipset system, this description
includes interrupt redirection.
Interrupts can originate from I/O(x)APIC devices or processors in the system.
Interrupts generated by I/O(x)APIC devices occur in the form of writes with a specific
address encoding. Interrupts generated by the processor appear on the processor bus
as transactions with a similar address encoding, and a specific encoding on the REQa/
REQb signals (REQa=01001, REQb=11100).
The XAPIC architecture provides for lowest priority delivery, through interrupt
redirection by the chipset. If the redirectable hint bit is set in the XAPIC message, the
chipset may redirect the interrupt to another processor. Note that redirection of
interrupts can be to any processor on either Processor Bus ID and can be applied to
both I/O interrupts and IPIs. The redirection can be performed in logical and physical
destination modes. For more details on the interrupt redirection algorithm, see
Section
XAPIC Interrupt Message Format
Interrupt messages have an address of 0x000_FEEz_zzzY. The 16-bit “zzzz” field
(destination field) determines the target to which the interrupt is being sent. The Y field
is mapped to A3 (redirectable interrupt) and A2 (destination mode). Figure 5-18 shows
the address definition in IA32 systems (XAPIC). For each interrupt there is only one data
transfer. The data associated with the interrupt message specifies the interrupt vector,
destination mode, delivery status, and trigger mode. The transaction type on the
processor bus is a request type of, interrupt transaction. The transaction type on the
PCI Express and ESI buses is a write. The address definition of Figure 5-18 applies to
5.5.3.
®
and Pentium
®
Pro processors.
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