R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 136

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 99 of 802
Table 6.19
X: 0 or 1; —: No change in outcome
Notes:
Port
P11_0
SCL
SSCK
(CLK2
INT0)
IVREF1
Port
P11_1
SSI
(RXD2
SCL2
TXD2
SDA2
INT1)
IVCMP1
Pin
Pin
1.
2.
3.
4.
5.
6.
7.
Pulled up by setting the corresponding bit in the P11PUR register to 1.
Output drive capacity high by setting the corresponding bit in the P11DRR register to 1.
N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1. At this time, set the PD11_0 bit in the PD11
register to 0.
N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1.
N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output) and setting the BIDE
bit to 0 (standard mode).
N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. At this time, set the PD11_1 bit in the PD11 register to 0.
Synchronous serial communication unit (refer to Table 26.4 Association between Communication Modes and I/O Pins).
Register
Register
i = 0
i = 1
Bit
Bit
Ports P11_0 and P11_1
PD11_i
PD11_i
PD11 INTSR
PD11 INTSR
X
X
X
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
SEL0
SEL0
INTi
INTi
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
INTiEN
INTiEN
INTEN
INTEN
Oct 30, 2009
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
INTCMP SSUIICSR ICCR1
INTCMP
INT1
INT1
CP0
CP0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
IICSEL
SSUIICSR
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
IICSEL
X
X
X
X
X
X
X
X
0
0
ICE
X
X
X
X
X
X
X
X
0
0
1
0
0
0
0
control
control
SSCK
output
output
SSU Associated
SSU Associated
SSI
X
X
X
X
X
X
X
Register
0
0
0
1
0
0
0
0
Register
0
0
0
1
0
0
0
0
0
0
control
control
SSCK
input
input
SSI
(7)
(7)
X
X
X
X
X
X
X
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
X X
X X
X X
X X
X X 1 0
X X 1 0 0
X X
X X
1 0 1 0
0 1
0 1
CLK2SEL0
RXD2
SEL
U2SR1
U2SR0
0
0
0
0
0
1
1
0
0
Other
Other
TXD2
than
than
10b
10b
SEL
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
0
1
1
X
X
2
2
U2MR
SMD
SMD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
1
1
1
1
U2MR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
1
0
0
U2SMR
CKDIR
IICM
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
1
0
0
0
1
Input port
Output port
SCL
input/output
SSCK input
SSCK output
CLK2 input
CLK2 output
INT0 input
Comparator B1
reference voltage
input (IVREF1)
Input port
Output port
SSI input
SSI output
RXD2 input
SCL2
input/output
TXD2 output
SDA2
input/output
INT1 input
Comparator B1
input (IVCMP1)
Function
Function
(1)
(1)
(1)
(1)
(1)
(2, 5)
(1)
(2)
(2)
(1)
(1)
(2, 6)
(2, 6)
(2)
(2, 4)
(2, 6)
(2, 3)
6. I/O Ports