R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 215

MCU FLASH 96+4KB 100LQFP

R5F2L3AAANFP#U1

Manufacturer Part Number
R5F2L3AAANFP#U1
Description
MCU FLASH 96+4KB 100LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet

Specifications of R5F2L3AAANFP#U1

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F2L3AAANFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 178 of 802
11.8
11.8.1
11.8.2
11.8.3
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the IR bit for the acknowledged interrupt is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is
acknowledged before setting a value in the SP, the program may run out of control.
Either the low-level width or high-level width shown in the Electrical Characteristics is required for the signal
input to pins INT0 to INT7 and pins KI0 to KI7, regardless of the CPU clock.
For details, refer to Table 34.23 Timing Requirements of External Interrupt INTi (i = 0 to 7) and Key
Input Interrupt KIi (i = 0 to 7).
Notes on Interrupts
Reading Address 00000h
SP Setting
External Interrupt, Key Input Interrupt
Oct 30, 2009
11. Interrupts

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