R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 659

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 622 of 802
Figure 28.6
Note:
Timer RA Set to pulse width measurement mode
Timer RA Set the pulse width measurement level to low
Timer RA Assign the TRAIO pin to P11_4
UART0
INT1
Timer RA Set the count source (f1, f2, f8, fOCO-S)
Timer RA Set the Synch Break width
Hardware LIN
Hardware LIN
Hardware LIN
Hardware LIN
Hardware LIN
1. When the previous communication completes normally and header field reception is
performed again with the same settings, the above settings can be omitted.
Bits TMOD2 to TMOD0 in TRAMR register 011b
TEDGSEL bit in TRAIOC register
Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register
Assign the RXD0 pin to P11_4
Bits RXD0SEL1 to RXD0SEL0 in U0SR register
Assign the INT1 pin to P11_4
INT4SEL0 bit in INTSR register
Bits TCK0 to TCK2 in TRAMR register
TRAPRE register
TRA register
Header Field Reception Flowchart Example (1)
Set the RXD0 input unmasking timing
(After Synch Break detection, or after Synch Field
measurement)
SBE bit in LINCR register
Set interrupts to enable
Bits BCIE, SBIE, SFIE in LINCR register
Set the LIN operation to stop
LINE bit in LINCR register
Set to slave mode
MST bit in LINCR register
Set the LIN operation to start
LINE bit in LINCR register
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Oct 30, 2009
A
1
0
0
1
0
10b
10b
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Set the TIOSEL bit in the
TRAIOC register to 1 to select the
hardware LIN function.
If the wake-up function is not
necessary, the setting of the INT4
pin can be omitted.
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after Synch Break
detection, the Synch Field signal is
also input to UART0.
28. Hardware LIN