R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 89

MCU FLASH 96+4KB 100LQFP

R5F2L3AAANFP#U1

Manufacturer Part Number
R5F2L3AAANFP#U1
Description
MCU FLASH 96+4KB 100LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet

Specifications of R5F2L3AAANFP#U1

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F2L3AAANFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 52 of 802
5.1
5.1.1
5.1.2
Notes:
1. The CWR bit is set to 0 (cold start-up) after power-on or exit from power-off mode. This bit remains unchanged at
2. When 1 is written to the CWR bit by a program, it is set to 1. (Writing 0 does not affect this bit.)
3. A hardware reset or an exit from power-off mode is detected.
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0004h
Address 000Bh
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM0 register.
a hardware reset, software reset, or watchdog timer reset.
Symbol
Symbol
Registers
Symbol
Symbol
Bit
Bit
PM03
CWR
HWR
SWR
WDR
Processor Mode Register 0 (PM0)
Reset Source Determination Register (RSTFR)
b7
b7
X
0
Reserved bits
Software reset bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Cold start-up/warm start-up
determine flag
Hardware reset detect flag
Software reset detect flag
Watchdog timer reset detect flag
Reserved bits
b6
b6
X
0
Oct 30, 2009
Bit Name
Bit Name
(2)
b5
b5
X
0
(3)
b4
b4
X
0
0: Cold start-up
1: Warm start-up
0: Not detected
1: Detected
0: Not detected
1: Detected
0: Not detected
1: Detected
When read, the content is undefined.
Set to 0.
Setting this bit to 1 resets the MCU. When read, the
content is 0.
PM03
WDR
b3
b3
0
0
SWR
b2
b2
0
0
Function
Function
HWR
b1
b1
X
0
CWR
b0
b0
X
0
(Note 1)
5. Resets
R/W
R/W
R/W
R/W
R/W
R
R
R
R

Related parts for R5F2L3AAANFP#U1